In recent years, in the through silicon via technology, there has been desired a technique of filling a metal into a via or through hole (minute space) provided on a semiconductor wafer (object to be processed). Because the Through Silicon Via Technology makes it possible to develop a chip stacking technology using through hole electrode, it is expected that a high-performance and high-speed semiconductor system is achieved by a three-dimensional stacked integrated circuit.
Further, as a method of filling a metal into a minute space formed on an object to be processed as mentioned above, the method disclosed in the Japanese Unexamined Patent Application Publication No. 2002-368083 is known, for example.
In the method disclosed in the Japanese Unexamined Patent Application Publication No. 2002-368083, in a pressure-reduced chamber, a molten metal is supplied onto a surface of a sample, on which a minute space to be filled with the molten metal is formed, so that the molten metal covers the minute space, and then the molten metal is vacuum sucked into the minute space by pressurizing the vacuum chamber to a pressure equal to or greater than atmospheric pressure using an inert gas. According to this method, the molten metal can be vacuum sucked into the minute space formed on the object to be processed by pressure difference generated between the inside of the minute space and the inside of the vacuum chamber.